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High-Speed USB 2.0 (480Mbps) DPST Switch with Overvoltage Protection (OVP) and Dedicated Charger Port Detection
ISL54226
The Intersil ISL54226 is a single supply, dual SPST (Single Pole/Single Throw) switch that is configured as a DPST. It can operate from a single 2.7V to 5.25V supply. The part was designed for switching or isolating a USB high-speed source or a USB high-speed and full-speed source in portable battery powered products. The 3.5 SPST switches were specifically designed to pass USB full speed and USB high-speed data signals. They have high bandwidth and low capacitance to pass USB high-speed data signals with minimal distortion. The ISL54226 has OVP detection circuitry on the COM pins to open the SPST switches when the voltage at these pins exceeds 3.8V or goes negative by -0.45V. It isolates fault voltages up to +5.25V or down to -5V from getting passed to the other side of the switch, thereby protecting the USB down-stream transceiver. The OE/ALM logic pin is an open drain input/output that can be driven to open the switches or monitored to tell when the part is in an overvoltage state. The part has an interrupt (INT) output pin to indicate a 1 to 1 (high/high) state on the COM lines to inform the processor when entering a dedicated charging port mode of operation. The ISL54226 is available in 8 Ld 1.2mmx1.4mm TQFN and 8 Ld 2mmx2mm TDFN packages. It operates over a temperature range of -40 to +85C.
ISL54226
Features
* High-Speed (480Mbps) and Full-Speed (12Mbps) Signaling Capability per USB 2.0 * 1.8V Logic Compatible (2.7V to +3.6V Supply) * OE/ALM Pin to Open all Switches and Indicate Overvoltage Fault Condition * Charger Interrupt Indicator Output * Power OFF Protection * COM Pins Overvoltage Protection for +5.25V and -5V Fault Voltages * -3dB Frequency . . . . . . . . . . . . . . . . . . . . 790MHz * Low ON Capacitance @ 240MHz . . . . . . . . . . . . 2pF * Low ON-Resistance . . . . . . . . . . . . . . . . . . . . 3.5 * Single Supply Operation (VDD) . . . . . 2.7V to 5.25V * Available in TQFN and TDFN Packages * Pb-Free (RoHS Compliant) * Compliant with USB 2.0 Short Circuit and Overvoltage Requirements without Additional External Components
Applications*(see page 16)
* MP3 and Other Personal Media Players * Cellular/Mobile Phones, PDA's * Digital Cameras and Camcorders * USB Switching
Typical Application
3.3V 500 VDD INT LOGIC OE/ALM CONTROL COM OVP DET COM + ISL54226 GND DUSB 4M D+ HIGH-SPEED TRANSCEIVER 3.3V 100k
USB 2.0 HS Eye Pattern with Switches in the Signal Path
VOLTAGE SCALE (0.1V/DIV)
USB CONNECTOR
VBUS D-
P
D+ GND
TIME SCALE (0.2ns/DIV)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54226
Pin Configurations
ISL54226 (8 LD 1.2x1.4 TQFN) TOP VIEW
7 GND 6 COM + 8 COM -
ISL54226 (8 LD 2x2 TDFN) TOP VIEW
PD INT 1 LOGIC D+ 2 4M 3 4 OVP 6 7 OE/ALM D8 VDD
OVP
D-
1 LOGIC
D+
5
COM+ GND
5 COM-
4M 2 3 VDD OE/ALM INT 4
NOTE: 1. Switches Shown for OE/ALM = Logic "0".
Pin Descriptions
TQFN TDFN 4 5 6 7 8 1 2 1 2 3 4 5 6 7 PIN NAME INT D+ COM+ GND COMDDESCRIPTION Charger Mode Interrupt Output USB Data Port USB Data Port Ground Connection USB Data Port USB Data Port
Truth Table
INPUT SIGNAL AT COM PINS 0V to 3.6V 0V to 3.6V Overvoltage Range Overvoltage Range COM Pins Tied Together COM Pins Tied Together OE/ALM 0 1 0 1 0 D-, D+ OFF ON OFF OFF OFF INT High High High High Low OUTPUT OE/ALM Low High Low Low Low STATE Normal Normal OVP OVP Charger Port (CP) Normal
OE/ALM Switch Enable/Alarm (Open Drain) Drive Low to Open Switches Outputs a Low when OTV is Activated VDD PD Power Supply Thermal Pad. Tie to Ground or Float
3 -
8 PD
1
ON
High
High
Logic "0" when 0.5V, Logic "1" when 1.4V with a 2.7V to 3.6V Supply.
TABLE 1. OVP TRIP POINT VOLTAGE SYSTEM VOLTAGE CONDITIONS CODEC SUPPLY 2.7V to 3.3V 2.7V to 3.3V SWITCH SUPPLY (VDD) 2.7V to 5.25V 2.7V to 5.25V COMs SHORTED TO VBUS -5V PROTECTED Yes Yes TRIP POINT MIN 3.62V -0.6V MAX 3.95V -0.29V
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Ordering Information
PART NUMBER (Notes 2, 5) ISL54226IRUZ-T (Note 4) ISL54226IRUZ-T7A (Note 4) ISL54226IRTZ-T (Note 3) ISL54226IRTZ-T7A (Note 3) ISL54226IRZEVAL1Z NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54226. For more information on MSL please see techbrief TB363. PART MARKING U5 U5 226 226 Evaluation Board TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE Tape & Reel (Pb-Free) 8 Ld 1.2mmx1.4mm TQFN 8 Ld 1.2mmx1.4mm TQFN 8 Ld 2mmx2mm TDFN 8 Ld 2mmx2mm TDFN PKG. DWG. # L8.1.4x1.2 L8.1.4x1.2 L8.2x2C L8.2x2C
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Absolute Maximum Ratings
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V VDD to COMx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5V COMx to Dx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6V Input Voltages D+, D- . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V COM+, COM- . . . . . . . . . . . . . . . . . . . . . . . -5V to 6.5V OE/ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V Continuous Current (COM - / D-, COM + / D+) . . . . 40mA Peak Current (COM-/D-, COM+/D+) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . 100mA ESD Rating: Human Body Model (Tested per JESD22-A114-F). . . . >2kV Machine Model (Tested per JESD22-A115-A) . . . . . . >150V Charged Device Model (Tested per JESD22-C101-D) . >2kV Latch-up (Tested per JEDEC; Class II Level A) . . . . at +85C
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 8 Ld TQFN Package (Notes 7, 9). . 210 165 8 Ld TDFN Package (Notes 6, 8). . . 96 19 Maximum Junction Temperature (Plastic Package). . +150C Maximum Storage Temperature Range. . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Normal Operating Conditions
Temperature Range . . . . . . VDD Supply Voltage Range . Logic Control Input Voltage Analog Signal Range VDD = 2.7V to 5.25V . . . . . . . . . . . . . . . -40C to +85C . . . . . . . . . . . . . 2.7V to 5.25V . . . . . . . . . . . . . . . 0V to 5.25V . . . . . . . . . . . . . . . . 0V to 3.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 9. For JC, the "case temp" location is taken at the package top center.
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40C to +85C.
PARAMETER TEST CONDITIONS TEMP MIN (C) (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS
ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON (High-Speed) VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or VCOM- = 0V to 400mV (see Figure 2, Note 15) 25 Full 25 Full 3.5 0.2 5 7 0.45 0.55
rON Matching Between VDD = 2.7V, OE/ALM = 1.4V, Channels, rON (High-Speed) IDx = 17mA, VCOM+ or VCOM- = Voltage at max rON, (Notes 14, 15) rON Flatness, RFLAT(ON) (High-Speed) ON-Resistance, rON VDD = 2.7V, OE/ALM = 1.4V, IDx = 17mA, VCOM+ or VCOM- = 0V to 400mV, (Notes 13, 15) VDD = 3.3V, OE/ALM = 1.4V, ICOMx = 17mA, VCOM+ or VCOM-= 3.3V (see Figure 2, Note 15) VDD = 5.25V, OE/ALM = 0V, VDx = 0.3V, 3.3V, VCOMX = 3.3V, 0.3V
25 Full +25 Full 25 Full 25 Full 25 25 25
-20 -9 -12 -
0.26 6.8 1 30 -
1 1.2 17 22 20 9 12 11 22 1
nA nA A A A A A
OFF Leakage Current, IDx(OFF)
ON Leakage Current, IDx(ON) VDD = 5.25V, OE/ALM = 5.25V, VDx = 0.3V, 3.3V, VCOMX = 0.3V, 3.3V Power OFF Leakage Current, ICOM+, ICOMPower OFF Logic Current, IOE/ALM Power OFF D+/D- Current, ID+, IDVDD = 0V, VCOM+ = 5.25V, VCOM- = 5.25V, OE/ALM = 0V VDD = 0V, OE/ALM = 5.25V VDD = 0V, OE/ALM = VDD, VD+ = VD- = 5.25V
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Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
PARAMETER Overvoltage Protection Detection Positive Fault-Protection Trip Threshold, VPFP VDD = 2.7V to 5.25V, OE/ALM = VDD (see Table 1 on page 2) 25 25 25 3.62 -0.6 3.8 -0.45 102 3.95 -0.29 V V ns TEST CONDITIONS TEMP MIN (C) (Notes 11, 12) TYP MAX (Notes 11, 12) UNITS
Negative Fault-Protection Trip VDD = 2.7V to 5.25V, OE/ALM = VDD Threshold, VNFP (see Table 1 on page 2) OFF Persistence Time Fault Protection Response Time Negative OVP Response: VDD = 2.7V, OE/ALM = VDD, VDx = 0V to -5V, RL = 1.5k Positive OVP Response: VDD = 2.7V, OE/ALM = VDD, VDx = 0V to 5.25V, RL = 1.5k ON Persistence Time Fault Protection Recovery Time VDD = 2.7V, OE/ALM = VDD , VDx = 0V to 5.25V or 0V to -5V, RL = 1.5k
25
-
2
-
s
25
-
45
-
s
DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Skew, (tSKEWOUT - tSKEWIN) VDD = 3.3V, VINPUT = 3V, RL = 50, CL = 50pF (see Figure 1) VDD = 3.3V, VINPUT = 3V, RL = 50, CL = 50pF (see Figure 1) VDD = 3.3V, OE/ALM = 3.3V, RL = 45, CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%) (see Figure 5) VDD = 3.3V, OE/ALM = 3.3V, RL = 45, CL = 10pF, (see Figure 5) VDD = 3.3V, RL = 50, f = 240MHz (see Figure 4) VDD = 3.3V, OE/ALM = 0V, RL = 50, f = 240MHz Signal = 0dBm, 0.86VDC offset, RL = 50 f = 1MHz, VDD = 3.3V, OE/ALM = 0V (see Figure 3) f = 1MHz, VDD = 3.3V, OE/ALM = 3.3V, (see Figure 3) f = 240MHz, VDD = 3.3V, OE/ALM = 3.3V 25 25 25 160 60 50 ns ns ps
Rise/Fall Degradation (Propagation Delay), tPD Crosstalk OFF-Isolation -3dB Bandwidth OFF Capacitance, COFF COM ON Capacitance, C(ON) COM ON Capacitance, C(ON)
25 25 25 25 25 25 25
-
250 -39 -23 790 2.5 4 2
-
ps dB dB MHz pF pF pF
POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 5.25V, OE/ALM = 5.25V Full 25 Full Positive Supply Current, IDD VDD = 3.6V, OE/ALM = 3.6V 25 Full Positive Supply Current, IDD VDD = 4.3V, OE/ALM = 2.6V 25 Full 2.7 45 23 35 5.25 56 59 30 34 45 50 V A A A A A A
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Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued)
PARAMETER Positive Supply Current, IDD TEST CONDITIONS VDD = 3.6V, OE/ALM = 1.4V TEMP MIN (C) (Notes 11, 12) 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VOE/ALML VDD = 2.7V to 3.6V Full Full Full Full Full Full Full Full 1.4 1.7 2.0 -8.2 1.4 0.5 0.7 0.8 V V V V V V nA A TYP 25 MAX (Notes 11, 12) UNITS 32 38 A A
Input Voltage High, VOE/ALMH VDD = 2.7V to 3.6V Input Voltage Low, VOE/ALML VDD = 3.7V to 4.2V
Input Voltage High, VOE/ALMH VDD = 3.7V to 4.2 Input Voltage Low, VOE/ALML VDD = 4.3V to 5.25V
Input Voltage High, VOE/ALMH VDD = 4.3V to 5.25V Input Current, IOE/ALML Input Current, IOE/ALMH NOTES: 10. VLOGIC = Input voltage to perform proper function. VDD = 5.25V, OE/ALM = 0V VDD = 5.25V, OE/ALM = 5.25V, 4M Pull-down
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 12. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value. 15. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
VDD LOGIC INPUT 50% 0V tOFF SWITCH INPUT VINPUT 90% SWITCH OUTPUT 0V tON VOUT 90% VIN VINPUT SWITCH INPUT COMx OE/ALM GND RL 50 CL 50pF Dx VOUT tr < 20ns tf < 20ns VDD C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (INPUT) R + r L ON FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
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Test Circuits and Waveforms (Continued)
VDD C
rON = V1/17mA
COMx
VHSDX V1 17mA OE/ALM VDD
Dx
GND
Repeat test for all switches.
FIGURE 2. rON TEST CIRCUIT
VDD C VDD C
COMx
SIGNAL GENERATOR OE/ALM 0V OR VDD GND ANALYZER RL
COM+
D+
50
IMPEDANCE ANALYZER Dx
OE/ALM VIN
DGND
COM-
NC
Repeat test for all switches. Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches.
FIGURE 3. CAPACITANCE TEST CIRCUIT
FIGURE 4. CROSSTALK TEST CIRCUIT
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Test Circuits and Waveforms (Continued)
VDD tri 90% DIN+ DIN10% 50% tskew_i 90% 50% 10% tfi tro 90% OUT+ OUT10% 50% tskew_o 90% tf0 50% 10% GND |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. DINDIN+ 143 15.8 143 COM+ D+ CL VDD 15.8 OE/ALM COMDCL OUT+ 45 OUT45 C
FIGURE 5A. MEASUREMENT POINTS FIGURE 5. SKEW TEST
FIGURE 5B. TEST CIRCUIT
Application Block Diagram
3.3V
3.3V 500 VDD INT 3.6V VBUS USB CONNECTOR >1M COM OVP DET COM + LOGIC CONTROL OE/ALM 4M DUSB HIGH-SPEED OR FULL-SPEED TRANSCEIVER CONTROLLER 100k
D-
D+ GND
D+
ISL54226
GND
PORTABLE MEDIA DEVICE
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Detailed Description
The ISL54226 device is a dual single pole/single throw (SPST) analog switch configured as a DPST that operates from a single DC power supply in the range of 2.7V to 5.25V. It was designed for switching a USB high-speed or full-speed source in portable battery powered products. It is offered in small TQFN and TDFN packages for use in MP3 players, cameras, PDAs, cellphones, and other personal media players. The part consists of two 3.5 high-speed SPST switches. These switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. They can also swing from 0V to 3.6V to pass USB full speed (12Mbps) differential data signals with minimal distortion. The part contains special overvoltage detection and protection (OVP) circuitry on the COM+ and COM- pins. This circuitry acts to open the USB in-line switches when the part senses a voltage on the COM pins that is >3.8V (typ) or < -0.45V (typ). It isolates voltages up to 5.25V and down to -5V from getting through to the other side of the switch to protect the USB transceiver connected at the D+ and D- pins. The device has an open drain OE/ALM pin that can be driven "Low" to open all switches. The OE/ALM pin gets internally pulled "Low" whenever the part senses an overvoltage condition. The pin must be externally pulled "High" with a 100k pull-up resistor and monitored for a "Low" to determine when an overvoltage condition has occurred. The part has charger port interrupt detection circuitry (CP) on the COM pins that outputs a Low on the INT pin to inform the Controller or power management circuitry when entering a dedicated charging port mode of operation. The charger mode operation is initiated by driving the OE/ALM pin Low and externally connecting the COM pins together which pulls the COM lines High, triggering the INT pin to go Low and the SPST switches to open. The ISL54226 was designed for MP3 players, cameras, cellphones, and other personal media player applications that need to switch a high-speed or full-speed transceiver source. A "Typical Application Block Diagram" of this functionality is shown on page 8. A detailed description of the SPST switches is provided in the following section.
between the switches over this signal range is only 0.2, ensuring minimal impact by the switches to USB high-speed signal transitions. As the signal level increases, the rON switch resistance increases. At signal level of 3.3V, the switch resistance is nominally 9.8. See Figures 9, 10, 11, 12, 13, 14 in the "Typical Performance Curves" beginning on page 12. The Dx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high-speed signal quality specifications. See Figure 15 in the "Typical Performance Curves" on page 13 for USB High-speed Eye Pattern taken with switch in the signal path. The Dx switches can also pass USB full-speed signals (12Mbps) in the range of 0V to 3.6V with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 16 in the "Typical Performance Curves" on page 14 for USB Full-speed Eye Pattern taken with switch in the signal path. The switches are active (turned ON) whenever the OE/ALM voltage is logic "1" (High) and OFF when the OE/ALM voltage is logic "0" (Low).
Overvoltage Protection (OVP)
The maximum normal operating signal range for the Dx switches is from 0V to 3.6V. For normal operation the signal voltage should not be allow to exceed these voltage levels or go below ground by more than -0.3V. However, in the event that a positive voltage >3.8V (typ) to 5.25V, such as the USB 5V VBUS voltage, gets shorted to one or both of the COM+ and COM- pins or a negative voltage < -0.45V (typ) to -5V gets shorted to one or both of the COM pins, the ISL54226 has OVP circuitry to detect the over voltage condition and open the SPST switches to prevent damage to the USB down-stream transceiver connected at the signal pins (D-, D+). The OVP and power-off circuitry allows the COM pins (COM-, COM+) to be driven up to 5.25V while the VDD supply voltage is in the range of 0V to 5.25V. In this condition the part draws <100A of ICOMx and IDD current and causes no stress to the IC. In addition the SPST switches are OFF and the fault voltage is isolated from the other side of the switch. The OE/ALM pin gets internally pulled low whenever the part senses an overvoltage condition. The pin must be externally pulled "High" with a 100k pull-up resistor and monitored for a "Low" to determine when an overvoltage condition has occurred. This output can be monitored by a Controller to indicate a fault condition to the system.
High-Speed (Dx) SPST Switches
The Dx switches are bi-directional switches that can pass USB high-speed and USB full-speed signals when VDD is in the range of 2.7V to 5.25V. When powered with a 2.7V supply, these switches have a nominal rON of 3.5 over the signal range of 0V to 400mV with a rON flatness of 0.26. The rON matching 9
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External VDD Series Resistor to Limit IDD Current during Negative OVP Condition
A 100 to 1k resistor in series with the VDD pin (see Figure 6) is required to limit the IDD current draw from the system power supply rail during a negative OVP fault event. With a negative -5V fault voltage at both com pins, the graph in Figure 7 shows the IDD current draw for different external resistor values for supply voltages of 2.7V, 3.6V, and 5.25V. Note: With a 500 resistor the current draw is limited to around 5mA. When the negative fault voltage is removed the IDD current will return to it's normal operation current of 25A to 45A. The series resistor also provides improved ESD and latch-up immunity. During an overvoltage transient event (such as occurs during system level IEC 61000 ESD testing), substrate currents can be generated in the IC that can trigger parasitic SCR structures to turn ON, creating a low impedance path from the VDD power supply to ground. This will result in a significant amount of current flow in the IC, which can potentially create a latch-up state or permanently damage the IC. The external VDD resistor limits the current during this overstress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation the low microamp IDD current of the IC produces an insignificant voltage drop across the series resistor resulting in no impact to switch operation or performance.
VSUPPLY 25 VCOM+ = VCOM- = -5V 20 IDD (mA) 15 10 5 0 100 3.6V 5.25V
2.7V
200
300
400
500 600 700 RESISTOR ()
800
900
1k
FIGURE 7. NEGATIVE OVP IDD CURRENT vs RESISTOR VALUE vs VSUPPLY
VSUPPLY
POWER MANAGEMENT BATTERY CHARGER CIRCUITRY "LOW" TO INDICATE CHARGER CONNECTED D+ DOE/ALM USB TRANCEIVER
VBUS
USB CONNECTOR
C
BATTERY CHARGER 200
D+ COM+ D-
VDD
CHG DET COMLOGIC GND
INT P DRIVEN LOW BY P (OE/ALM = "0")
GND
PROTECTION RESISTOR 100 TO 1k COM+ -5V FAULT VOLTAGE COMVDD OVP
C IDD D+ DOE/ALM GND INT LOW TO INDICATE OVP 100k
FIGURE 8. CHARGER PORT DETECTION
CHARGER PORT DETECTION The ISL54226 has special charger port detection circuitry that monitors the voltage at the com pins to detect when a battery charger has been connected into the USB port (see Figure 8). When the battery charger is connected to the USB connector it shorts the COM+ and COM- pins together. The shorting of the pins is sensed by the ISL54226 IC and it pulls the COM+ and COM- lines high and as long as the OE/ALM pin is driven low (OE/ALM = "0") by the P, it will drive its INT logic output "Low" to tell the power management circuitry that a battery charger is connected at the port and not a USB host transceiver. The power management circuitry will then set the appropriate current level and use the USB connector VBUS line to charge the battery.
LOGIC
FIGURE 6. VDD SERIES RESISTOR TO LIMIT IDD CURRENT DURING NEGATIVE OVP AND FOR ENHANCED ESD AND LATCH-UP IMMUNITY
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ISL54226 Operation
The following will discuss using the ISL54226 shown in the "Application Block Diagram" on page 8.
TABLE 2. LOGIC CONTROL VOLTAGE LEVELS VDD SUPPLY RANGE 2.7V to 3.6V LOGIC = "0" (LOW) OE/ALM 0.5V or floating 0.7V or floating 0.8V or floating LOGIC = "1" (HIGH) OE/ALM 1.4V
Power
The power supply connected at the VDD pin provides the DC bias voltage required by the ISL54226 part for proper operation. The ISL54226 can be operated with a VDD voltage in the range of 2.7V to 5.25V. For lowest power consumption you should use the lowest VDD supply. A 0.01F or 0.1F decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. In a typical application, VDD will be in the range of 2.8V to 4.3V and will be connected to the battery or LDO of the portable media device.
3.7V to 4.2V
1.7V
4.3V to 5.25V
2.0V
Normal Operation Mode
With a signal level in the range of 0V to 3.6V the switches will be ON when the OE/ALM pin = Logic "1" and will be OFF (high impedance) when the OE/ALM pin = Logic "0".
Logic Control
The state of the ISL54226 device is determined by the voltage at the OE/ALM pin and the signal voltage at the COM pins. Refer to "Truth Table" on page 2. The OE/ALM pin is internally pulled low through 4M resistors to ground and can be tri-stated by a Processor. The OE/ALM pin is an open drain connection. It should be pulled high through an external 100k pull-up resistor. The OE/ALM pin can then be driven "Low" by a Processor to open all switches or it can be monitored by the Processor for a "Low" when the part goes into an overvoltage condition. The ISL54226 is designed to minimize IDD current consumption when the logic control voltage is lower than the VDD supply voltage. With VDD = 3.6V and the OE/ALM logic pin is at 1.4V the part typically draws only 25A. With VDD = 4.3V and the OE/ALM logic pin is at 2.6V the part typically draws only 35A. Driving the logic pin to the VDD supply rail minimizes power consumption. The OE/ALM pin can be driven with a voltage higher than the VDD supply voltage. It can be driven up to 5.25V with a VDD supply in the range of 2.7V to 5.25V.
USB 2.0 VBUS Short Requirements
The USB specification in section 7.1.1 states a USB device must be able to withstand a VBUS short (4.4V to 5.25V) or a -1V short to the D+ or D- signal lines when the device is either powered off or powered on for at least 24 hours. The ISL54226 part has special power-off protection and OVP detection circuitry to meet these short circuit requirements. This circuitry allows the ISL54226 to provide protection to the USB down-stream transceiver connected at its signal pins (D-, D+) to meet the USB specification short circuit requirements. The power-off protection and OVP circuitry allows the COM pins (COM-, COM+) to be driven up to 5.25V or down to -5V while the VDD supply voltage is in the range of 0V to 5.25V. In these overvoltage conditions with a 500 external VDD resistor the part draws <55A of current into the COM pins and causes no stress/damage to the IC. In addition all switches are OFF and the shorted VBUS voltage will be isolated from getting through to the other side of the switch channels, thereby protecting the USB transceiver.
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FN7614.0 July 29, 2010
ISL54226
Typical Performance Curves
3.4 ICOM = 17mA 3.3 2.7V
TA = +25C, Unless Otherwise Specified
16 14 12 ICOM = 17mA
rON ()
rON ()
3.2
3.0V 3.3V
10 8 6 4 2 0 0 0.6 1.2 1.8 VCOM (V) 5.25V 2.4 3.0V
2.7V
3.1
3.6V 4.3V
3.0
5.25V
3.3V
2.9
0
0.1
0.2 VCOM (V)
0.3
0.4
3.0
3.6
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
4.5 4.0
V+ = 2.7V ICOM = 17mA +85C
18
V+ = 2.7V 16 ICOM = 17mA 14 12 rON () +25C 10 8 6 4 2 -40C +85C +25C
3.5 rON () 3.0 2.5 2.0 1.5 0
-40C
0.1
0.2 VCOM (V)
0.3
0.4
0
0
0.5
1.0
1.5 2.0 VCOM (V)
2.5
3.0
3.5
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
4.0 +85C 3.5
9 8 7 6 V+ = 3.3V ICOM = 17mA
rON ()
3.0
rON ()
+25C
5 4
+85C +25C
2.5 V+ = 3.3V ICOM = 17mA 2.0 0 0.1
-40C
3 2
-40C
0.2 VCOM (V)
0.3
0.4
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.6
VCOM (V)
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
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FN7614.0 July 29, 2010
ISL54226
Typical Performance Curves
TA = +25C, Unless Otherwise Specified (Continued)
VDD = 3.3V
VOLTAGE SCALE (0.1V/DIV)
TIME SCALE (0.2ns/DIV)
FIGURE 15. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
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FN7614.0 July 29, 2010
ISL54226
Typical Performance Curves
VDD = 3.3V
TA = +25C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.5V/DIV)
TIME SCALE (10ns/DIV)
FIGURE 16. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
0.0
5.0 4.5
-0.5 IOH CURRENT (mA)
VDD = 3.3V IOL CURRENT (mA)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
VDD = 5.25V
-1.0
-1.5 VDD = 5.25V -2.0
VDD = 3.3V
-2.5
0
1
2
3
4
5
0.0
0
1
2
3
4
5
VOH VOLTAGE (V)
VOL VOLTAGE (V)
FIGURE 17. IOH vs VOH vs VDD for INT
FIGURE 18. IOL vs VOL vs VDD for INT
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FN7614.0 July 29, 2010
ISL54226
Typical Performance Curves
1 0 NORMALIZED GAIN (dB)
TA = +25C, Unless Otherwise Specified (Continued)
-10 -20 NORMALIZED GAIN (dB) -30 -40 -50 -60 -70 -80 -90 RL = 50 VIN = 0dBm, 0.2VDC BIAS
-1 -2 -3 -4
RL = 50 VIN = 0dBm, 0.86VDC BIAS
-100 1M 10M 100M 1G -110 0.001 0.01 0.1 1M 10M 100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. FREQUENCY RESPONSE
FIGURE 20. OFF-ISOLATION
-10 -20 -30
NORMALIZED GAIN (dB)
RL = 50 VIN = 0dBm, 0.2VDC BIAS
Die Characteristics
SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP):
-40 -50 -60 -70 -80 -90
GND
TRANSISTOR COUNT:
1297
PROCESS:
Submicron CMOS
-100 -110 0.001 0.01 0.1 1M 10M 100M 500M
FREQUENCY (Hz)
FIGURE 21. CROSSTALK
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FN7614.0 July 29, 2010
ISL54226
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 7/29/10 REVISION FN7614.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL54226 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7614.0 July 29, 2010
ISL54226
Package Outline Drawing
L8.2x2C
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD Rev 0, 07/08
2.00
6 PIN 1 INDEX AREA
A B
8
0.50 2.00
6 PIN #1 INDEX AREA
1
1.450.050 Exp.DAP
(4X)
0.15
0.10 M C A B
0.25
( 8x0.30 )
TOP VIEW
0.800.050 Exp.DAP
Package Outline
( 8x0.20 ) ( 8x0.30 )
BOTTOM VIEW
SEE DETAIL "X"
( 6x0.50 )
1.45
2.00
0 . 75 ( 0 . 80 max)
0.10 C
C
BASE PLANE
SEATING PLANE 0.08 C
( 8x0.25 ) 0.80 2.00
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
C
0 . 2 REF
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN7614.0 July 29, 2010
ISL54226
Package Outline Drawing
L8.1.4x1.2
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/09
0.80 REF 4X 0.40 BSC 1.40 PIN 1 INDEX AREA A B 6
PIN 1 8
INDEX AREA
1.20
5
C0.10
0.30 1 0.40
0.60 0.10 2X 0.40 BSC 4 2 0.10 M C A B 0.05 M C 4 8 X 0.20 7X 0.30 0.05
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X" 0.80 REF 4X 0.40 PKG OUTLINE MAX. 0.50
0.10
C C
SEATING PLANE 8 X 0.20 0.08 C
SIDE VIEW
0.60 0.60 7X 0.50 C 0.70 0.60 0-0.05 0 . 2 REF
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
18
FN7614.0 July 29, 2010

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